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Preliminary Technical Data
FEATURES
Dual, 14-16 Bit nanoDACTM with 5ppm/C OnChip Reference in MSOP AD5643R/AD5663R
FUNCTIONAL BLOCK DIAGRAM
VDD LDAC SCLK INTERFACE LOGIC INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB VREF 1.25/2.5V Ref DAC REGISTER STRING DAC A
Low power dual 14-16-bit nanoDAC On-chip 1.25/2.5V, 5ppm/C Reference 10-lead MSOP and 3mmx3mm LFCSP package Power-down to 480 nA @ 5 V, 100 nA @ 3 V 3 V /5 V power supply Guaranteed 16-bit monotonic by design 3 power-down functions Hardware /LDAC and /CLR functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility
INPUT REGISTER
BUFFER
VOUTA
SYNC
DIN
AD5643R/AD5663R
POWER-ON RESET
POWER-DOWN LOGIC
LDAC CLR
GND
Figure 1.
APPLICATIONS
Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
RELATED DEVICES Part No. AD5663
Description 2.7V to 5.5V 16-bit DAC , external reference
GENERAL DESCRIPTION
The AD5643/63R, a member of the nanoDAC family, is a low power, dual, 14-16-bit buffered voltage-out DAC that operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5663R has an on-chip reference with an internal gain of two. The AD5643/AD5663-3 has a 1.25V 5ppm/C reference giving a fullscale output of 2.5V and the AD5643/AD5663-5 have a 2.5V 5ppm/C reference giving a fullscale output of5V. The on-board reference is off at power-up allowing the use of an external reference. The internal reference is turned on by writing to the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in powerdown mode.The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The AD5643/AD5663R's on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5643R/AD5663R uses a versatile 3-wire serial interface that operates at clock rates up to 50 MHz, and is compatible with standard SPI(R), QSPITM, MICROWIRETM, and DSP interface standards.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. Dual 14-16-bit DAC On-chip 1.25/2.5V, 5ppm/C Reference Available in 10-lead MSOP and 10-lead 3mmx3mm LFCSP package. Low power. Typically consumes 0.42 mW at 3 V and 0.75 mW at 5 V. 10 s max settling time.
5.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD5643R/AD5663R
TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Characteristics..................................................................... 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Description ............................ 11 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 19 D/A Section................................................................................. 19 Resistor String ............................................................................. 19 Output Amplifier........................................................................ 19 Serial Interface ............................................................................ 19 Input Shift Register..................................................................... 20
Preliminary Technical Data
SYNC Interrupt .......................................................................... 20 Power-On Reset.......................................................................... 20 Power-Down Modes .................................................................. 22 Microprocessor Interfacing....................................................... 24 Applications..................................................................................... 27 Using a Reference as a Power Supply for the AD5643/AD5663R..................................................................... 27 Bipolar Operation Using the AD5643/AD5663R .................. 28 Using AD5643/AD5663Rwith a Galvanically Isolated Interface ................................................. 28 Power Supply Bypassing and Grounding................................ 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 31
REVISION HISTORY
Xx/05--Revision 0: Initial Version
Rev. PrA | Page 2 of 33
Preliminary Technical Data AD5643R/AD5663R-5 SPECIFICATIONS
AD5643R/AD5663R
(VDD = +4.5 V to +5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = Vdd; all specifications TMIN to TMAX unless otherwise noted) Table 1.
Parameter STATIC PERFORMANCE2 AD5663R Resolution Relative Accuracy Differential Nonlinearity AD5643R Resolution Relative Accuracy Differential Nonlinearity Load Regulation Zero Code Error Offset Error Full-Scale Error Gain Error Zero Code Error Drift3 Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk6 (Ext Ref) A Grade B Grade Unit B Version 1 Conditions/Comments
16 32 1 16 32 1 2 +2 +10 10 -0.15 -1 1. 5 2 2.5 -100 10 4.5 -10 20 9 -20 0 VDD 2 10 0.5 30 4 VDD 40 75 0.75 VDD 150
16 tbd 1 16 tbd 1 2 +2 +10 10 -0.15 -1 1. 5 2 2.5 -100 10 4.5 -10 20 9 -20 0 VDD 2 10 0.5 30 4 VDD 40 75 0.75 VDD 150
Bits min LSB max LSB max Bits min LSB max LSB max LSB/mA mV typ mV max mV max % of FSR typ % of FSR max % of FSR max V/C typ ppm typ dB typ V V/mA V V V/mA V V min V max nF typ nF typ typ mA typ s typ V A typ A max V min V max k
Guaranteed Monotonic by Design.
Guaranteed Monotonic by Design. VDD=Vref=5V, Midscale Iout=0mA to 15mA sourcing/sinking All Zeroes Loaded to DAC Register
All Ones Loaded to DAC Register.
of FSR/C DAC code = midscale; VDD = 5V 10% RL = 2 k. to GND or VDD Due to Load current change Due to Powering Down (per channel) RL = 2 k. to GND or VDD Due to Load current change Due to Powering Down (per channel)
DC Crosstalk6 (Int Ref)
OUTPUT CHARACTERISTICS3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short Circuit Current Power-Up Time REFERENCE INPUTS3 Reference Input voltage Reference Current Reference Input Range Reference Input Impedance
RL= RL=2 k VDD=+5V Coming Out of Power-Down Mode. VDD=+5V 1% for specified performance VREF = VDD = +5.5V
Per DAC channel
1 2
Temperature Range: A grade (-40C to +105C); B grade (-40C to +105C); Y grade (-40C to +125C) Linearity calculated using a reduced code range: AD5663R( Code 512 to code 65024) . Output unloaded. 3 Guaranteed by design and characterization, not production tested. Reference input range at ambient where 1 LSB max DNL specification is achievable. Rev. PrA | Page 3 of 33
AD5643R/AD5663R
Parameter REFERENCE OUTPUT Output Voltage Reference TC Output Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD=4.5 V to +5.5 V VDD=4.5 V to +5.5 V IDD (All Power-Down Modes) VDD=4.5 V to +5.5 V VDD=4.5 V to +5.5 V POWER EFFICIENCY IOUT/IDD A Grade 2.495 2.505 10 2 2 0.8 2 3 4.5 5.5 1 3 0.48 1 90 B Grade 2.495 2.505 10 2 2 0.8 2 3 4.5 5.5 1 3 0.48 1 90 Unit V min V max ppm/C max k typ A max V max V min pF typ V min V max mA typ mA max A typ A max % At ambient
Preliminary Technical Data
B Version 1 Conditions/Comments
All digital inputs VDD=+5 V VDD=+5 V
All Digital Inputs at 0 or VDD DAC Active and Excluding Load Current VIH=VDD and VIL=GND VIH=VDD and VIL=GND VIH=VDD and VIL=GND VIH=VDD and VIL=GND ILOAD=2 mA, VDD=+5 V
Rev. PrA | Page 4 of 33
Preliminary Technical Data AC CHARACTERISTICS1
AD5643R/AD5663R
(VDD = +4.5 V to +5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = Vdd; all specifications TMIN to TMAX unless otherwise noted)
Parameter2 Output Voltage Settling Time Settling Time for 1LSB Step Slew Rate Digital-to-Analog Glitch Impulse Channel -to-Channel Isolation Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise
NOTES
1Guaranteed
Min
Typ 8 1.5 10 100 0.5 0.5 1 3 200 -80 120 100 15
Max 10
Unit s V/s nV-s dB nV-s nV-s nV-s nV-s kHz dB nV/Hz nV/Hz Vp-p
B Version 1 Conditions/Comments 1/4 to 3/4 scale settling to 2LSB
1 LSB Change Around Major Carry.
VREF = 2V 0.1 V p-p. VREF = 2V 0.1 V p-p. Frequency = 10kHz DAC code=8400H, 1kHz DAC code=8400H, 10kHz 0.1Hz to 10Hz;
by design and characterization; not production
Rev. PrA | Page 5 of 33
AD5643R/AD5663R
AD5643R/AD5663R-3 SPECIFICATIONS
Table 2.
Parameter STATIC PERFORMANCE2 AD5664R Resolution Relative Accuracy Differential Nonlinearity Load Regulation Zero Code Error Offset Error Full-Scale Error Gain Error Zero Code Error Drift3 Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk6 (Ext Ref) A Grade B Grade Unit
Preliminary Technical Data
(VDD1 = +2.7 V to +3.6 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = Vdd; all specifications TMIN to TMAX unless otherwise noted)
B Version 1 Conditions/Comments
16 32 1 2 +2 +10 10 -0.15 -1 1. 5 2 2.5 -100 10 4.5 -10
16 tbd 1 2 +2 +10 10 -0.15 -1 1. 5 2 2.5 -100 10 4.5 -10 20 9 -20 0 VDD 2 10 0.5 30 4 VDD 30 50 0.75 VDD 150 1.248
Bits min LSB max LSB max LSB/mA mV typ mV max mV max % of FSR typ % of FSR max % of FSR max V/C typ ppm typ dB typ V V/mA V V V/mA V V min V max nF typ nF typ typ mA typ s typ V A typ A max V min V max k V min
Guaranteed Monotonic by Design. VDD=Vref=3V, Midscale Iout=0mA to 7.5mA sourcing/sinking All Zeroes Loaded to DAC Register
All Ones Loaded to DAC Register.
of FSR/C DAC code = midscale; VDD = 3V 10% RL = 2 k. to GND or VDD Due to Load current change Due to Powering Down (per channel) RL = 2 k. to GND or VDD Due to Load current change Due to Powering Down (per channel)
DC Crosstalk6 (Int Ref)
20 9 -20
OUTPUT CHARACTERISTICS3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short Circuit Current Power-Up Time REFERENCE INPUTS3 Reference Input voltage Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage
0 VDD 2 10 0.5 30 4 VDD 30 50 0.75 VDD 150 1.248
RL= RL=2 k VDD=+5V Coming Out of Power-Down Mode. VDD=+5V 1% for specified performance VREF = VDD = +3.6V
Per DAC channel At ambient
1 Temperature Range: A grade (-40C to +105C); B grade (-40C to +105C); Y grade (-40C to +125C) 1Part is functional with VDD supply up to 5.5V 2 Linearity calculated using a reduced code range: ( Code 512 to code 65024. Output unloaded. 3 Guaranteed by design and characterization, not production tested. Reference input range at ambient where 1 LSB max DNL specification is achievable.
Rev. PrA | Page 6 of 33
Preliminary Technical Data
Reference TC Output Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD=2.7 V to +3.6 V VDD=2.7 V to +3.6 V IDD (All Power-Down Modes) VDD=2.7 V to +3.6 V VDD=2.7 V to +3.6 V POWER EFFICIENCY IOUT/IDD 1.252 10 2 2 0.8 2 3 2.7 3.6 1 3 0.48 1 90 1.252 10 2 2 0.8 2 3 2.7 3.6 1 3 0.48 1 90 V max ppm/C max k typ A max V max V min pF typ V min V max mA typ mA max A typ A max %
AD5643R/AD5663R
All digital inputs VDD=+3 V VDD=+3 V
All Digital Inputs at 0 or VDD DAC Active and Excluding Load Current VIH=VDD and VIL=GND VIH=VDD and VIL=GND VIH=VDD and VIL=GND VIH=VDD and VIL=GND ILOAD=2 mA, VDD=+3 V
Rev. PrA | Page 7 of 33
AD5643R/AD5663R
AC CHARACTERISTICS1
Preliminary Technical Data
(VDD = +2.7 V to +3.6 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = Vdd; all specifications TMIN to TMAX unless otherwise noted)
Parameter2 Output Voltage Settling Time Settling Time for 1LSB Step Slew Rate Digital-to-Analog Glitch Impulse Channel -to-Channel Isolation Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise
NOTES
1Guaranteed 2See
Min
Typ 8 1.5 10 100 0.5 0.5 1 3 200 -80 120 100 15
Max 10
Unit s V/s nV-s dB nV-s nV-s nV-s nV-s kHz dB nV/Hz nV/Hz Vp-p
B Version 1 Conditions/Comments 1/4 to 3/4 scale settling to 2LSB
1 LSB Change Around Major Carry.
VREF = 2V 0.1 V p-p. VREF = 2V 0.1 V p-p. Frequency = 10kHz DAC code=8400H, 1kHz DAC code=8400H, 10kHz 0.1Hz to 10Hz;
by design and characterization; not production tested. the Terminology section.
Rev. PrA | Page 8 of 33
Preliminary Technical Data TIMING CHARACTERISTICS
AD5643R/AD5663R
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. (VDD = +2.7 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)
Parameter t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Limit at TMIN, TMAX VDD = 2.7 V to 3.6 V VDD= 3.6 V to 5.5 V 20 11 9 13 4 4 0 25 13 0 20 20 20 0 20 9 9 13 4 4 0 20 13 0 20 20 20 0 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SYNC Rising Edge to SCLK Fall Ignore SCLK Falling Edge to SYNC Fall Ignore LDAC Pulsewidth Low SCLK Falling Edge to LDAC Rising Edge /CLR Pulse Width Low SCLK Falling Edge to LDAC Falling Edge
t10 SCLK t8 SYNC t6 t5 DIN DB31 t4 t3
t1
t9
t2
t7
DB0 t14 t11
LDAC1 t12 LDAC2 t13
CLR
NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE. 2. SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
1
3Maximum SCLK frequency is 50 MHz at VDD = +2.7 V to +5.5 V Rev. PrA | Page 9 of 33
AD5643R/AD5663R
ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VOUT to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Industrial (A, B Version) Automotive (Y Version) Storage Temperature Range Junction Temperature (TJ max) Power Dissipation LFCSP Package (4-Layer Board) JA Thermal Impedance MSOP Package (4-Layer Board) JA Thermal Impedance JC Thermal Impedance Reflow Soldering Peak Temperature Pb-free Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +105C -40C to +125C -65C to +150C 150C (TJ max - TA)/JA 61C/W 142C/W 43.7C/W 260C 5C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 10 of 33
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTION
VOUTA VOUTB GND LDAC CLR
1 10
AD5643R/AD5663R
AD5663R
2 3 4 5 9
VREF VDD DIN SCLK SYNC
TOP VIEW (Not to Scale)
8 7 6
Figure 3. MSOP and LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic VOUTA VOUTB GND /LDAC CLR Function Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. Asynchronous Clear Input. TheCLR input is falling edge sensitive and Active low. While CLRis low all LDAC pulses are ignored. When CLR is activated, Zeroscale is loaded to All Input and DAC Registers. This clears the output to 0V. The part will exit Clear code mode on the 32nd falling edge of the next write to the part. If CLRis activated during a write sequence the write will be aborted. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND.
6
SYNC
7 8 9 10
SCLK DIN VDD
VREFIN/VREFOUT
The AD56x3R has a common reference input/reference output Pin. When the internal reference is selected this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
Rev. PrA | Page 11 of 33
AD5643R/AD5663R
TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
TBD
TBD
Figure 4. Typical INL Plot Figure 8. INL and DNL Error vs. VREF
TBD
TBD
Figure 5. Typical DNL Plot Figure 9. INL and DNL Error vs. Supply
TBD
TBD
Figure 6. Typical Total Unadjusted Error Plot
Figure 10. Gain Error and Full-Scale Error vs. Temperature
TBD
Figure 7. INL Error and DNL Error vs. Temperature
Rev. PrA | Page 12 of 33
Preliminary Technical Data
AD5643R/AD5663R
Figure 14. IDD Histogram with VDD = 5.5 V
TBD TBD
Figure 11. Zero-Scale and Offset Error vs. Temperature Figure 15. Headroom at Rails vs. Source and Sink Current
TBD
TBD
Figure 12. Gain Error and Full-Scale Error vs. Supply Figure 16. Supply Current vs. Code
TBD
TBD
Figure 13. Zero-Scale and Offset Error vs. Supply Figure 17. Supply Current vs. Temperature
TBD
Rev. PrA | Page 13 of 33
AD5643R/AD5663R
Preliminary Technical Data
TBD
TBD
Figure 18. Supply Current vs. Supply Voltage
Figure 21. Full-Scale Settling Time, 5 V
TBD
TBD
Figure 19. Supply Current vs. Logic Input Voltage
Figure 22. Power-On Reset to 0 V
TBD
TBD
Figure 20. Full-Scale Settling Time, 3 V
Figure 23. Power-On Reset to Midscale
Rev. PrA | Page 14 of 33
Preliminary Technical Data
AD5643R/AD5663R
TBD
TBD
Figure 24. Exiting Power-Down to Midscale
Figure 28. Total Harmonic Distortion
TBD TBD
Figure 25. Digital-to-Analog Glitch Impulse (Negative)
Figure 29. Settling Time vs. Capacitive Load
TBD
TBD
Figure 26. Digital-to-Analog Glitch Impulse (Positive)
TBD
Figure 30. 0.1 Hz to 10 Hz Output Noise Plot
Figure 27. Digital Feedthrough
Rev. PrA | Page 15 of 33
AD5643R/AD5663R
Preliminary Technical Data
Figure 31. Noise Spectral Density
TBD
Rev. PrA | Page 16 of 33
Preliminary Technical Data TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 5. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5664 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 11. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure 10. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measurement of the output error, taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure 6. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Offset Error Offset error is a measure of the difference between V OUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5664 with code 512 loaded in the DAC register. It can be negative or
positive.
AD5643R/AD5663R
DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by 10%. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the 24th falling edge of SCLK.
Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x10000). See Figure 25 and Figure 26. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.
Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (voltage per Hz). It is measured by loading the DAC to midscale and meas-
uring noise at the output. It is measured in nV/Hz. A plot of Noise Spectral Density can be seen in Figure 31.
DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a fullscale output change on one DAC while monitoring another DAC kept at midscale. It is expressed in V. Channel-to-Channel Isolation This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and
Rev. PrA | Page 17 of 33
AD5643R/AD5663R
vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another
Preliminary Technical Data
DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
Rev. PrA | Page 18 of 33
Preliminary Technical Data THEORY OF OPERATION
D/A SECTION
The AD5643R/AD5663R DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 32 shows a block diagram of the DAC architecture.
VDD REF (+) DAC REGISTER RESISTOR STRING REF () OUTPUT AMPLIFIER (Gain=2) VOUT
AD5643R/AD5663R
R
R
R
TO OUTPUT AMPLIFIER
GND
Figure 32. DAC Architecture
R
D VOUT = Vrefin x 2^ N
when using an external reference;
Figure 33. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 15. The slew rate is 1.5 V/s with a 1/4 to 3/4 full-scale settling time of 10 s.
D VOUT = 2 Vrefout x 2^ N
when using the internal reference; where D = decimal equivalent of the binary code that is loaded to the DAC register; 0 to 65535 for AD5663R (16 bit) 0 to 16383 AD5643R (14 bit) N = the DAC resolution
INTERNAL REFERENCE
The AD5643R/AD5663R have an on-chip reference with an internal gain of two. The AD56x3R-3 has a 1.25V 10ppm/C max reference giving a fullscale output of 2.5V and the AD56x3R-5 has a 2.5V 10ppm/C max reference giving a fullscale output of 5V. The on-board reference is off at powerup allowing the use of an external reference. The internal reference is enabled via a write to a control register The internal reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads When using the internal reference, it is recommended that a 100nF capacitor is placed between reference output and GND for reference stability.
RESISTOR STRING
The resistor string section is shown in Figure 33. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
SERIAL INTERFACE
The AD5643R/AD5663R has a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Error! Reference source not found. for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the
Rev. PrA | Page 19 of 33
04777-023
Since the input coding to the DAC is straight binary, the ideal output voltage is given by:
R
AD5643R/AD5663R
falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5643R/AD5663R compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. As mentioned previously it must, however, be brought high again just before the next write sequence.
Preliminary Technical Data
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see figure 37).
POWER-ON RESET
The AD5643R/AD5663R contains a power-on reset circuit that controls the output voltage during power-up. The AD5643R/AD5663R DAC outputs power up to 0 V and the output remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. Any events on LDAC or CLR during power-on-reset are ignored.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see figure 34). The first two bits are don't cares. The next three are the Command bits C2 - C0, (see Table 1) followed by the 3-bit DAC address A2A0, (see Table 2) and finally the 16-bit data word. The data word comprises the 16 bit input code. See figure 34. The data bits are transferred to the DAC register on the 24th falling edge of SCLK.
Software Reset
The AD5643R/AD5663R contains a Software Reset function. Command 101 is reserved for the Software Reset function, see Table 1. The Software Reset command contains two reset modes that are software-programmable by setting bit DB0 in the control register. Table 5 shows how the state of the bit corresponds to the mode of operation of the device.
Table 5. Software Reset Modes for the AD5664
Software Reset Mode DB0 0 1 (Power-on -Reset) Registers reset to zero DAC Register Input Register DAC Register Input Register /LDAC Register Powerdown Register Internal Reference Setup Register
DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
DB0 (LSB) D1 D0
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 34.AD5663R Input Register Contents
Rev. PrA | Page 20 of 33
Preliminary Technical Data
SCLK
AD5643R/AD5663R
SYNC
DIN
DB23
DB0
DB23
DB0
04777-025
INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE
Figure 37 SYNC Interrupt Facility
C2 0 0 0 0 1 1 1 1
C1 0 0 1 1 0 0 1 1
C0 0 1 0 1 0 1 0 1
Command Write to Input Register n Update DAC Register n Write to Input Register n, Update All Write to and Update DAC channel n Power Down DAC (Power-up) Reset (Power-on-Reset) Load LDAC Register Internal Reference Setup (On/Off)
Table 1. Command Definition
A2 0 0 0 0 1
A1 0 0 1 1 1
A0 0 1 0 1 1
ADDRESS (n) DAC A DAC B Reserved Reserved All DACs
Table 2. Address Command
Rev. PrA | Page 21 of 33
AD5643R/AD5663R
POWER-DOWN MODES
Preliminary Technical Data
The AD5643R/AD5663R contains four separate modes of operation. Command 100 is reserved for the Power-Down function. See Table 1. These modes are software-programmable by setting two bits (DB5 and DB4) in the control register. Table 6 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs, (DacB and DacA) may be powered down to the selected mode by setting the corresponding 2 bits (DB1,andDB 0) to a "1". By executing the same Command 100, any combination of DACs may be powered up by setting the bits (DB5 and DB4) to Normal Operation mode. Again, to select which combination of DAC channels to power-up set the corresponding 2 bits (DB1 and DB 0) to a "1". See Table 7 for contents of the Input Shift Register during power down/up operation. The DAC output will power-up to the value in the input register while /LDAC is low. If /LDAC is high, the DAC ouput will power-up to the value held in the DAC register before power-down. Table 6. Modes of Operation for the AD5643/AD5663R
DB5 0 0 1 1
MSB
DB4 0 1 0 1
Operating Mode Normal Operation Power-Down Modes 1 k to GND 100 k to GND Three-State
LSB
DB23 - DB22 x
DB21
DB20
DB19
DB18
DB17
DB16
DB15-- DB6 x
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
x
x
x
PD1
PD0
x
x
DacB
DacA
Don't Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A2 - A0) Don't cares
Don't Cares
Power Down Mode
Don't Cares
Power Down/Up Channel Selection - Set Bit to a "1" to select channel
Table 7. 24-Bit Input Shift Register Contents of Power Up/Down Function for the AD5643/AD5663R When both bits are set to 0, the part works normally with its normal power consumption of 500 A at 5 V. However, for the three powerdown modes, the supply current falls to 480 nA at 5 V (100 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 k or 100 k resistor, or left open-circuited (three-state) (see figure 35).
RESISTOR STRING DAC
AMPLIFIER
VOUT
POWER-DOWN CIRCUITRY
Figure 35. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 s for VDD = 5 V and for VDD = 3 V (see Figure 24).
Rev. PrA | Page 22 of 33
04777-026
RESISTOR NETWORK
Preliminary Technical Data
LDAC FUNCTION
AD5643R/AD5663R
The outputs of all DACs may be updated simultaneously using the hardware /LDAC pin. Synchronous LDAC: The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse. LDAC can be permanently low or pulsed as in Figure 1. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. Alternatively, a software LDACfunction is available . Command 010 is reserved f or this software LDAC function - write to input register n and update all. An LDAC register gives the user extra flexibility and control over the hardware LDAC pin. This register allows the user to select which combination of channels to simultaneously update when the hardware LDAC pin is executed. Setting the LDAC bit register to a "0" for a DAC channel means that this channels' update will be controlled by the LDAC pin. If this bit is set to a "1" then this channel will synchronously update, that is the DAC register is updated after new data is read in regardless of the state of the /LDAC pin It effectively sees the LDAC pin as being pulled low. See Table 8 for the LDAC register mode of operation. This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating Writing to the DAC using command 110,loads the 2-bit /LDAC register (DB1-DB0) The default for each channel is "0" ie LDAC pin works normally. Setting the bits to a "1" means the DAC channel will be updated regardless of the state of the LDAC pin. See Table 9 for contents of the Input Shift Register during the load LDAC register mode of operation.
Load DAC Register LDACBITS (DB1DB0) 0 1 LDAC PIN 1/0 x - Don't Care LDAC Operation Determined by LDAC pin DAC channels will update, overwriting the LDACpin. DAC channels see LDAC as 0
Table 8. LDAC Register Definition
MSB
LSB
DB23 - DB22 x
DB21
DB20
DB19
DB110
DB17
DB16
DB15 - DB2
DB1
DB0
1
1
0
x
x
x
x
DacB
DacA
Don't Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A3 - A0) Don't cares
Don't Cares
Setting /LDAC bit to "1" overwrites /LDAC pin
Table 9. 24-Bit Input Shift Register Contents for /LDAC Overwrite Function
INTERNAL REFERENCE SETUP
The on-board reference is off at power-up by default. This allows the use of an external reference if the application requires it. The
Rev. PrA | Page 23 of 33
AD5643R/AD5663R
Preliminary Technical Data
AD5643R/AD5663R-3 have a 1.25V 10ppm/C max reference giving a fullscale output of 2.5V and the AD5643R/AD5663R -5 have a 2.5V 10ppm/C max reference giving a fullscale output of 5V. The on-board reference can be turned on/off by a user programmable REF Setup register by setting the bit DB0 high or low, see Table 3. Command 111 is reserved for this Internal REF Setup command, see Table 1. Error! Reference source not found.4 shows how the state of the bits in the Input Shift Register corresponds to the mode of operation of the device.
Internal Reference Setup Register (DB0) 0 1
Action Reference Off (Default) Reference On
Table 3. Reference Set-up Register
MSB
LSB
DB23 - DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15DB1
DB0
x Don't Cares
1
1
1
x
x
x
x Don't Cares
1/0 Reference Setup Register
COMMAND BITS (C2-C0)
ADDRESS BITS (A2- A0)
Table 4 32-Bit Input Shift Register Contents for Reference Setup Function
MICROPROCESSOR INTERFACING
AD5643R/AD5663R to Blackfin(R) ADSP-BF53X Interface
Figure 36 shows a serial interface between the AD5643R/AD5663R and the Blackfin ADSP-BF53X microprocessor. The ADSP-BF53X processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5643/AD5663R, the setup for the interface is as follows. DT0PRI drives the DIN pin of the AD5643/AD5663R, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0.
ADSP-BF53X*
Figure 36. AD5643R/AD5663R to Blackfin ADSP-BF53X Interface
AD5643R/AD5663R to 68HC11/68L11 Interface
Figure 37 shows a serial interface between the AD5643R/AD5663R and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5643/AD5663R, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows. The 68HC11/68L11 is configured with its CPOL bit as a 0 and its CPHA bit as a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/ 68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5643/AD5663R, PC7 is left low after the first eight bits are
AD5662*
TFS0 DTOPRI TSCLK0
SYNC DIN SCLK
04777-027
*ADDITIONAL PINS OMITTED FOR CLARITY
Rev. PrA | Page 24 of 33
Preliminary Technical Data
transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure.
68HC11/68L11*
AD5643R/AD5663R
AD5662*
PC7 SCK MOSI
SYNC SCLK DIN
04777-028
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. AD5643R/AD5663R to 68HC11/68L11 Interface
Rev. PrA | Page 25 of 33
AD5643R/AD5663R
AD5643R/AD5663R to 80C51/80L51 Interface
Figure 38 shows a serial interface between the AD5643R/AD5663R and the 80C51/80L51 microcontroller. The setup for the interface is as follows. TXD of the 80C51/80L51 drives SCLK of the AD5643/AD5663R, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5643/AD5663R, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes only; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5643R/AD5663R must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account.
80C51/80L51*
Preliminary Technical Data
AD5643R/AD5663R to MICROWIRE Interface
Figure 39 shows an interface between the AD5643R/AD5663R and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5643R/AD5663R on the rising edge of the SK.
MICROWIRE*
AD5662*
CS SK SO
SYNC SCLK DIN
04777-030
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 39. AD5643R/AD5663R to MICROWIRE Interface
AD5662*
P3.3 TXD RXD
SYNC SCLK DIN
04777-029
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 38. AD5643R/AD5663R to 80C51/80L51 Interface
Rev. PrA | Page 26 of 33
Preliminary Technical Data APPLICATIONS
USING A REFERENCE AS A POWER SUPPLY FOR THE AD5643/AD5663R
Because the supply current required by the AD5643R/AD5663R is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 40). This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5643/AD5663R; see Error! Reference source not found. for a suitable reference. If the low dropout REF195 is used, it must supply 500 A of current to the AD5643/AD5663R, with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 k load on the DAC output) is 500 A + (5 V/5 k) = 1.25 mA
AD5643R/AD5663R
The load regulation of the REF195 is typically 2 ppm/mA, which results in a 3 ppm (15 V) error for the 1.5 mA current drawn from it. This corresponds to a 0.196 LSB error.
+15V +5V
REF195
SYNC THREE-WIRE SERIAL INTERFACE SCLK DIN
VDD
VOUT = 0V TO 5V
AD5664
Figure 40. REF195 as Power Supply to the AD5624R/AD5644R/AD5664
Rev. PrA | Page 27 of 33
AD5643R/AD5663R
BIPOLAR OPERATION USING THE AD5663R
The AD5663R has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 41. The circuit gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
D R1 + R2 R2 VO = VDD x x - VDD x 65,536 R1 R1
POWER
Preliminary Technical Data
5V REGULATOR 10F 0.1F
VDD SCLK V1A VOA SCLK
ADMu1300
AD56x0
VOB SYNC VOUT
SDI
V1B
10 x D VO = -5 V 65,536
Figure 42. AD5663R with a Galvanically Isolated Interface
This is an output voltage range of 5 V, with 0x0000 corresponding to a -5 V output, and 0xFFFF corresponding to a +5 V output.
R2 = 10k +5V +5V R1 = 10k AD820/ OP295 VDD 10 F 0.1 F VOUT -5V 5V
AD5664
THREE-WIRE SERIAL INTERFACE
Figure 41. Bipolar Operation with the AD5663R
USING AD5663R WITH A GALVANICALLY ISOLATED INTERFACE
In process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the DAC is functioning. iCoupler(R) provides isolation in excess of 2.5 kV. The AD5663R use a 3-wire serial logic interface, so the ADuM1300 three-channel digital isolator provides the required isolation (see Figure 42). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5663R.
Rev. PrA | Page 28 of 33
04539-053
where D represents the input code in decimal (0 to 65535). With VDD = 5 V, R1 = R2 = 10 k,
DATA
V1C
VOC
DIN GND
Preliminary Technical Data
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5663R should have separate analog and digital sections, each having its own area of the board. If the AD5663R is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5663R. The power supply to the AD5663R should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be located as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor has low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of
AD5643R/AD5663R
capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
Rev. PrA | Page 29 of 33
AD5643R/AD5663R
OUTLINE DIMENSIONS
INDEX AREA
Preliminary Technical Data
3.00 BSC SQ
10
PIN 1 INDICATOR
1
1.50 BCS SQ
TOP VIEW
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
2.48 2.38 2.23
5
6
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 TYP
SIDE VIEW
0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF
1.74 1.64 1.49
0.30 0.23 0.18
Figure 43. . 10-Lead Lead Frame Chip Scale Package (CP-10-9) Dimensions shown in millimeters
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
Figure 44. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
Rev. PrA | Page 30 of 33
Preliminary Technical Data
ORDERING GUIDE
Package Description Model AD5663RBRMZ-3 AD5663RBCPZ-3 AD5663RARMZ-5 AD5663RBRMZ-5 AD5643RBRMZ-3 AD5643RARMZ-5 AD5643RBRMZ-5 Temperature Range -40C to +105C -40C to +125C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C 10-lead MSOP 10-lead LFCSP 10-lead MSOP 10-lead MSOP 10-lead MSOP 10-lead MSOP 10-lead MSOP Package Option RM-10 CP-10 RM-10 RM-10 RM-10 RM-10 RM-10
AD5643R/AD5663R
Internal Reference
1.25V 1.25V 2.5V 2.5V 1.25V 2.5V 2.5V
Acurracy 16 LSB INL 16 LSB INL 32 LSB INL 16 LSB INL 16 LSB INL 32 LSB INL 16 LSB INL
Rev. PrA | Page 31 of 33
AD5643R/AD5663R
NOTES
Preliminary Technical Data
Rev. PrA | Page 32 of 33
Preliminary Technical Data NOTES
AD5643R/AD5663R
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR05858-0-11/05(PrA)
Rev. PrA | Page 33 of 33

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